BCD Decoder Logic

logic friday screen shot

7 Segment decoder full truth table. Note that RBI’ segment decoders are
exactly the same except in the A=B=C=D=0 condition

Here is my original truth table for the encoder. It features 7 segmenmt
decoding of a BCD input from 0-9. It also features Ripple Blanking
input and output much like the standard TTL Decoders of the day which
basically will cause the diplay to NOT show a ‘0’ if RBI’ is low.

Caution ASCII art ahead!

         
         a
        ----
       |    |
      f| g  |b 
       |----|
       |    |
      e|    |c
       |----|
         d

So for the number 1 segments b + c are active, for the number 5 segments
a + f + g + c + d are active, you get the idea…

The truth table was taken from the 7447 and 9368 latch-decoder-driver. I had
intentions of implementing the full hex display but with the extra
decoding the gate (relay) count gets way to high. This also does NOT
include the latch, just decoding.

0 = Low or in relay logic off but not ground (in my mind)
1 = active so V+
X = Don't care let the logic minimizer do it's
    magic to reduce gates.

A - MSB
...
D - LSB

   INPUTS               |   OUTPUTS
#  RBI' A   B   C   D   |   a b c d e f g RBO'
------------------------+---------------------
0   0   0   0   0   0   |   0 0 0 0 0 0 0  0
1   0   0   0   0   1   |   0 1 1 0 0 0 0  1
2   0   0   0   1   0   |   1 1 0 1 1 0 1  1
3   0   0   0   1   1   |   1 1 1 1 0 0 1  1
4   0   0   1   0   0   |   0 1 1 0 0 1 1  1
5   0   0   1   0   1   |   1 0 1 1 0 1 1  1
6   0   0   1   1   0   |   1 0 1 1 1 1 1  1
7   0   0   1   1   1   |   1 1 1 0 0 0 0  1
8   0   1   0   0   0   |   1 1 1 1 1 1 1  1
9   0   1   0   0   1   |   1 1 1 0 0 1 1  1
10  0   1   0   1   0   |   X X X X X X X  X
11  0   1   0   1   1   |   X X X X X X X  X
12  0   1   1   0   0   |   X X X X X X X  X
13  0   1   1   0   1   |   X X X X X X X  X
14  0   1   1   1   0   |   X X X X X X X  X
15  0   1   1   1   1   |   X X X X X X X  X
16  1   0   0   0   0   |   1 1 1 1 1 1 0  1
17  1   0   0   0   1   |   0 1 1 0 0 0 0  1
18  1   0   0   1   0   |   1 1 0 1 1 0 1  1
19  1   0   0   1   1   |   1 1 1 1 0 0 1  1
20  1   0   1   0   0   |   0 1 1 0 0 1 1  1
21  1   0   1   0   1   |   1 0 1 1 0 1 1  1
22  1   0   1   1   0   |   1 0 1 1 1 1 1  1
23  1   0   1   1   1   |   1 1 1 0 0 0 0  1
24  1   1   0   0   0   |   1 1 1 1 1 1 1  1
25  1   1   0   0   1   |   1 1 1 0 0 1 1  1
26  1   1   0   1   0   |   X X X X X X X  X
27  1   1   0   1   1   |   X X X X X X X  X
28  1   1   1   0   0   |   X X X X X X X  X
29  1   1   1   0   1   |   X X X X X X X  X
30  1   1   1   1   0   |   X X X X X X X  X
31  1   1   1   1   1   |   X X X X X X X  X
------------------------+---------------------

This table below is the optimized version where don’t care conditions
have been filled in to minimize the logic. Yes, lots of magic that is
being done by the ‘Logic Friday’.

   INPUTS               |  OUTPUTS
#  RBI' A   B   C   D   |  a b c d e f g RBO'
------------------------+--------------------
0   0   0   0   0   0   |  0 0 0 0 0 0 0  0
1   0   0   0   0   1   |  0 1 1 0 0 0 0  1
2   0   0   0   1   0   |  1 1 0 1 1 0 1  1
3   0   0   0   1   1   |  1 1 1 1 0 0 1  1
4   0   0   1   0   0   |  0 1 1 0 0 1 1  1
5   0   0   1   0   1   |  1 0 1 1 0 1 1  1
6   0   0   1   1   0   |  1 0 1 1 1 1 1  1
7   0   0   1   1   1   |  1 1 1 0 0 0 0  1
8   0   1   0   0   0   |  1 1 1 1 1 1 1  1
9   0   1   0   0   1   |  1 1 1 0 0 1 1  1
10  0   1   0   1   0   |  1 1 1 1 1 1 1  1
11  0   1   0   1   1   |  1 1 1 1 0 1 1  1
12  0   1   1   0   0   |  1 1 1 1 1 1 1  1
13  0   1   1   0   1   |  1 1 1 1 0 1 1  1
14  0   1   1   1   0   |  1 1 1 1 1 1 1  1
15  0   1   1   1   1   |  1 1 1 0 0 1 1  1
16  1   0   0   0   0   |  1 1 1 1 1 1 0  1
17  1   0   0   0   1   |  0 1 1 0 0 0 0  1
18  1   0   0   1   0   |  1 1 0 1 1 0 1  1
19  1   0   0   1   1   |  1 1 1 1 0 0 1  1
20  1   0   1   0   0   |  0 1 1 0 0 1 1  1
21  1   0   1   0   1   |  1 0 1 1 0 1 1  1
22  1   0   1   1   0   |  1 0 1 1 1 1 1  1
23  1   0   1   1   1   |  1 1 1 0 0 0 0  1
24  1   1   0   0   0   |  1 1 1 1 1 1 1  1
25  1   1   0   0   1   |  1 1 1 0 0 1 1  1
26  1   1   0   1   0   |  1 1 1 1 1 1 1  1
27  1   1   0   1   1   |  1 1 1 1 0 1 1  1
28  1   1   1   0   0   |  1 1 1 1 1 1 1  1
29  1   1   1   0   1   |  1 1 1 1 0 1 1  1
30  1   1   1   1   0   |  1 1 1 1 1 1 1  1
31  1   1   1   1   1   |  1 1 1 0 0 1 1  1
------------------------+---------------------

Here is the expanded table as done by Logic Friday. It has the don’t
care values worked in for what I’m guessing is optimization purposes.
If you have not messed with ‘Logic Friday’ it’s a free logic
designer with very nice optimizations as well as circuit creation.

INPUTS               |   OUTPUTS
RBI' A   B   C   D   |   a b c d e f g RBO'
---------------------+---------------------
X    1   X   X   X   |   1 0 0 0 0 0 0  0
X    X   X   1   X   |   1 0 0 0 0 0 0  0
X    X   1   X   1   |   1 0 0 0 0 0 0  0
1    X   0   X   0   |   1 0 0 0 0 0 0  0
X    1   X   X   X   |   0 1 0 0 0 0 0  0
X    X   0   1   X   |   0 1 0 0 0 0 0  0
X    X   0   X   1   |   0 1 0 0 0 0 0  0
X    X   X   1   1   |   0 1 0 0 0 0 0  0
X    X   1   0   0   |   0 1 0 0 0 0 0  0
1    X   X   0   0   |   0 1 0 0 0 0 0  0
X    1   X   X   X   |   0 0 1 0 0 0 0  0
X    X   1   X   X   |   0 0 1 0 0 0 0  0
X    X   X   X   1   |   0 0 1 0 0 0 0  0
1    X   X   0   X   |   0 0 1 0 0 0 0  0
X    X   0   1   X   |   0 0 0 1 0 0 0  0
X    1   X   X   0   |   0 0 0 1 0 0 0  0
X    X   X   1   0   |   0 0 0 1 0 0 0  0
X    X   1   0   1   |   0 0 0 1 0 0 0  0
1    X   0   X   0   |   0 0 0 1 0 0 0  0
X    1   X   X   0   |   0 0 0 0 1 0 0  0
X    X   X   1   0   |   0 0 0 0 1 0 0  0
1    X   0   X   0   |   0 0 0 0 1 0 0  0
X    1   X   X   X   |   0 0 0 0 0 1 0  0
X    X   1   0   X   |   0 0 0 0 0 1 0  0
X    X   1   X   0   |   0 0 0 0 0 1 0  0
1    X   X   0   0   |   0 0 0 0 0 1 0  0
X    1   X   X   X   |   0 0 0 0 0 0 1  0
X    X   0   1   X   |   0 0 0 0 0 0 1  0
X    X   1   0   X   |   0 0 0 0 0 0 1  0
X    X   X   1   0   |   0 0 0 0 0 0 1  0
1    X   X   X   X   |   0 0 0 0 0 0 0  1
X    1   X   X   X   |   0 0 0 0 0 0 0  1
X    X   1   X   X   |   0 0 0 0 0 0 0  1
X    X   X   1   X   |   0 0 0 0 0 0 0  1
X    X   X   X   1   |   0 0 0 0 0 0 0  1
---------------------+--------------------

Digital Friday has been kind enough to minimize the logic to –

a = A  + C + B D + RBI' B' D';
b = A  + B' C + B' D + C D + B C' D' + RBI' C' D';
c = A  + B  + D + RBI' C' ;
d = B' C + A D' + C D' + B C' D + RBI' B' D';
e = A D' + C D' + RBI' B' D';
f = A + B C' + B D' + RBI' C' D';
g = A + B' C + B C' + C D';
RBO' = RBI'  + A  + B  + C  + D;

RBO' means NOT RBO if you havent already guessed.

So for BCD Values (ABCD) of 0-9 the decode has expected output, but for values
of 10-15 the segment values are what ever the software minimizer deems
necessary for reducing the gate count.

As a side note playing around with the displayed segments makes a good
bit of differences (no pun intended) on the gate count. For example if
the value for ‘9’ is segments a+b+c+f+g for a display of –

Yes, caution more ASCII art…

         a
        ----
       |    |
      f| g  |b 
       |----|
            |
            |c
            |
            

vs. the fancy nine as I’ll call it using segments a+b+c+d+f+g –

         a
        ----
       |    |
      f| g  |b 
       |----|
            |
            |c
        ----|
         d

The gate count rises by a few gates. Which translates into a bunch
more relay.

My math for mapping gates to SPDT relays =

Inverter : 1 Relay
2 Input AND, OR, NAND, NOR : 2 Relays
3 Input AND, OR, NAND, NOR : 3 Relays

And so on, so a few more gates adds up the relay count a bunch.

The gate count for the circuit is 25. Total relays including 7 extra for output
buffers end up being 58. The output buffers are a good idea as it will allow
a completely decouple switch from the logic voltage as well as providing a way
to blank the entire display with one line.

I’m going to optimize also for a display of 0-5 for digital clock use. This
alone should cut the gate count down in addition in removing the need for
RBI’/RBO lines. It may not be implemented in copper but here it is.

Here is the minimized decoder for 0-5 digits

a = B + A C + A' C';
b = A' + C';
c = B' + C;
d = B + A C + A' C';
e = A' C';
f = A + B' C';
g = A + B ;

    INPUTS      |  OUTPUTS
#   A   B   C   |  a b c d e f g
----------------+----------------
0   0   0   0   |  1 1 1 1 1 1 0
1   0   0   1   |  0 1 1 0 0 0 0
2   0   1   0   |  1 1 0 1 1 0 1
3   0   1   1   |  1 1 1 1 0 0 1
4   1   0   0   |  0 1 1 0 0 1 1
5   1   0   1   |  1 0 1 1 0 1 1
6   1   1   0   |  1 1 0 1 0 1 1
7   1   1   1   |  1 0 1 1 0 1 1
----------------+----------------

Note again that this is a ‘Logic Friday’ optimized table. The last two
values of 6 and 7 can’t be displayed and were set as don’t care (X).
Digital Friday sets these to minimize the logic to eliminate the gates.

Total gate count is 10, and for SPDT relays adds up to about 26 including
7 buffer relays on the output to isolate the drivers (not shown).
58 Relays, and the Hex decoder requires
26.

Now some digital clock math –

Seconds digits (hex + decade)      = 26 + 58 = 84 
Minutes digits (hex + decade)      = 26 + 58 = 84 
Hours Digits   (SPECIAL* + decade) =  2 + 58 = 60
==================================================
Total Display relays                         = 228

*SPECIAL :
For the Most Significant Hours digit, that can display as blanked, or 1.
The segments for the ‘1’ digit can be connected together and one relay
can turn it on or off, then add another relay for the output buffer and
we are at 2.

So it looks like the plan will be to make a decade digit display with
a few extra relays (2 at least) and the hours +10 digit can be fit on
the same board.

Initial design will need 2 boards, 1 decimal, one hex for an optimized route
with a decade decoder and a hex decoder. It may be just be cheaper to do all
one run of the decade decoder pcb’s and forgo the cost of extra relays for the
specialized hex decoder board.

So that is the ugly installment of the progress on the relay clock. Next is schematics!

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One Response to BCD Decoder Logic

  1. Sandy Ganz June 16, 2015 at 8:55 pm #

    Some updates on the project. While I have not updated the site, I have completed the PCB and have a completed BCD Relay decoder. Any bugs? Yes, but only on a part of the circuit that is optional and could be easily fixed in V2.0 if I do another run of the boards. Overall it seems to work!!

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